Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Reducing the CMOS RAM test complexity with IDDQ and voltage testing
Journal of Electronic Testing: Theory and Applications
Separate IDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis
Journal of Electronic Testing: Theory and Applications
Identifying defects in deep-submicron CMOS ICs
IEEE Spectrum
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique
Proceedings of the IEEE International Test Conference on Test and Design Validity
IDDQ Characterization in Submicron CMOS
Proceedings of the IEEE International Test Conference
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
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The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the levelof the precharge. A technique to test open defects producingdata retention faults is proposed. An initial condition is forced during the writingphase. In this way, intermediate voltages appear duringthe memorizing phase. Hence,the quiescent current consumption (I_DDQ)increases and the fault can be detected sensing the I_DDQ. The testability regions for the defective memory cell were determined using state diagrams. Conditions to obtain the optimum vectorhave been stated. A DFT circuitry has been proposed. The cost ofthe proposed approach in terms of area, test time, and performancedegradation is analyzed.