Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
A 370-MHz memory built-in self-test state machine
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Design-for-Current-Testability (DFCT) for Dynamic CMOS Logic
Design-for-Current-Testability (DFCT) for Dynamic CMOS Logic
Testing for multiple faults in domino-CMOS logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The Limits of Digital Testing for Dynamic Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Methodology for the McKinley Processor
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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Dynamic logic fails differently than static logic.Fault modeling with Quad Differential Cascode VoltageSwitch (DCVS) is studied in simulation and hardware.Appropriate test methods are examined yielding resultsrelevant to general dynamic logic, DCVS, and pass gateDCVS.