A 256Meg SDRAM BIST for Disturb Test Application

Authors:
Theo J. Powell;Francis Hii;Dan Cline
Affiliations:
-;-;-
Venue:
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Year:
1997

Citing 3
Cited 0

Testing semiconductor memories: theory and practice

Testing semiconductor memories: theory and practice
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM

Proceedings of the IEEE International Test Conference on Test and Design Validity
A built in self test scheme for 256Meg sdram

MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)

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Abstract

The Disturb Test Algorithms are targeted for rowadjacent coupled defects that can be time elapseddependent. A BIST design is described for application ofthese tests for testing 256Meg SDRAM chips.