Semiconductor manufacturing process monitoring using built-in self-test for embedded memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Tutorial: Characterizing SDRAMS
MTDT '99 Proceedings of the 1999 IEEE International Workshop on Memory Technology, Design, and Testing
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Process optimization in a manufacturing environment for dynamic random access devices (DRAMS) can be improved using fail bit maps in production. Since fail bit maps for 64 Mbit, 256 Mbit and 1 Gbit are quite huge, it is difficult to generate, store and analyze these maps in a manufacturing environment. This paper presents a new scheme for generating compressed bit fail maps during test or from full bit fail maps with minimum loss of fail pattern information. Construction of the special compression scheme for a typical memory array with typical fail patterns will be shown. The described method has been successfully implemented for a 64 Mbit DRAM in a manufacturing environment compressing the bit fail maps to 2 kBit, allowing classification of 13 fail types.