Data structures and network algorithms
Data structures and network algorithms
Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Architectural Yield Optimization for WSI
IEEE Transactions on Computers
Introduction to VLSI Systems
Chips on wafers, or packing rectangles into grids
Computational Geometry: Theory and Applications - Special issue on the 19th European workshop on computational geometry - EuroCG 03
Chips on wafers, or packing rectangles into grids
Computational Geometry: Theory and Applications - Special issue on the 19th European workshop on computational geometry - EuroCG 03
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Wafer packing is a process of combining multiple chip designs on the same wafer such that the fabrication cost can be shared by several designs and hence reduced. This technique is widely used for designs that require a small number of dies or chips. It is essential to have computer algorithms to decide how to allocate designs to wafers in order to reduce the total fabrication cost. Based on different wafer fabrication techniques, two versions of the wafer packing problem are formulated. The authors study different variations for each version. They present algorithms to find optimal solutions for these variations which are polynomial-time solvable. They also present heuristic algorithms for those proven to be NP-hard. The effectiveness of the proposed algorithms is demonstrated by experimental results.