Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Area-Efficient VLSI Layouts for Binary Hypercubes
IEEE Transactions on Computers
Efficient VLSI Layouts of Hypercubic Networks
FRONTIERS '99 Proceedings of the The 7th Symposium on the Frontiers of Massively Parallel Computation
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
A complexity theory for VLSI
Efficient low-degree interconnection networks for parallel processing: topologies, algorithms, vlsi layouts, and fault tolerance
AT2L2 o N2/2 for fast fourier transform in multilayer VLSI
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
Hi-index | 0.00 |
In this paper we study the square grid area required for laying out Hl, the Boolean hypercube of N = 2l vertices. It is shown that this area is 4/9N2 + o(N2). We describe a layout which occupies this much area and prove that no layout of less area exists.