On the Lower Bound to the VLSI Complexity of Number Conversion from Weighted to Residue Representation

Authors:
G. Alia;E. Martinelli
Affiliations:
-;-
Venue:
IEEE Transactions on Computers
Year:
1993

Citing 4
Cited 0

Area-time optimal VLSI integer multiplier with minimum computation time

Information and Control
Area-time lower-bound techniques with applications to sorting

Algorithmica
A VLSI Modulo m Multiplier

IEEE Transactions on Computers
A complexity theory for VLSI

A complexity theory for VLSI

Quantified Score

Hi-index	14.98

Visualization

Abstract

A lower bound AT/sup 2/= Omega (n/sup 2/) for the conversion from positional to residue representation is derived according to VLSI complexity theory, and existing solutions for the same problem are briefly reviewed in the light of such a bound. A VLSI system is proposed, one that operates according to a pipeline scheme and works asymptotically emulating an optimal structure, independently of residue number system parameters. This solution has been applied to a design of specific size (64-b input stream), and it has been found that a single CMOS custom chip can implement the design with a throughput of one residue representation every 30-40 ns.