Parallel VLSI computation of all shortest paths in a graph

Authors:
Sujit Dey;Pradip K. Srimani
Affiliations:
Department of Computer Science, Southern Illinois University, Carbondale, IL;Department of Computer Science, Southern Illinois University, Carbondale, IL
Venue:
CSC '88 Proceedings of the 1988 ACM sixteenth annual conference on Computer science
Year:
1988

Citing 4
Cited 0

Parallel graph algorithms

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A complexity theory for VLSI

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Abstract

We present a new parallel algorithm to solve the all-pairs shortest path problem in a given graph which is considerably faster than the most recently published algorithm [7] for the same problem. Next we propose a suitable VLSI systolic architecture to map our algorithm and evaluate the performance of the proposed architecture in terms of execution time and interprocessor communication time. We show that our implementation has O(log2n) execution time (compare-exchange time) and O(n log n) communication time compared to O(n log n) and O(n2) in [7].