Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
Data Manipulating Functions in Parallel Processors and Their Implementations
IEEE Transactions on Computers
| Hi-index | 0.00 |
For applications requiring irregular forms of addressing, the high speed of operation of present day random-access memories and large-scale-integrated arithmetic structures can hardly lead to any significant improvements over conventional techniques unless appropriate means are used for addressing the operands at comparable speeds. This paper proposes the architecture for an integrated indexing unit intended for high-speed generation of the addressing patterns required for a wide range of such applications. Reference is made to the usefulness of the proposed unit for the organization of fast array processing attachments to conventional minicomputers and microcomputers.