Resource allocation in rectangular SW banyans
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A hardware support mechanism for scheduling resources in a parallel machine environment
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Processor-memory interconnections for multiprocessors
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Study of multistage SIMD interconnection networks
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
A Self Managing Secondary Memory system
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
A varistructured fail-soft cellular computer
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
A dynamically reconfigurable distributed computing system.
A dynamically reconfigurable distributed computing system.
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Staged circuit switching for network computers
SIGCOMM '83 Proceedings of the symposium on Communications Architectures & Protocols
| Hi-index | 0.00 |
The problems of resource allocation, configuration and reconfiguration and network control must be solved before reconfigurable array computers can be effectively utilized. The interconnection networks proposed for these systems vary so that there has been no common or optimal solution proposed to these problems. This paper defines and describes the objectives, design, implementation and use of a network controller for a reconfigurable array computer, the Texas Reconfigurable Array Computer (TRAC). The objectives for the network controller are defined by management of the system state, the requirements of the operating system for functionality and the interface the network presents to the operating system. These objectives may be expected to have at least some commonality across most reconfigurable network architectures. The structure of the network controller given herein may offer guidance for development of controllers for other reconfigurable network architectures.