Performance analysis of redundant-path networks for multiprocessor systems

Authors:
Krishnan Padmanabhan;Duncan H. Lawrie
Affiliations:
Digital Architectures Research Department, AT&T Bell Laboratories, Murray Hill, NJ;Center for Supercomputing Research and Development, University of Illinois, Urbana, IL
Venue:
ACM Transactions on Computer Systems (TOCS)
Year:
1985

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Abstract

Performance of a class of multistage interconnection networks employing redundant paths is investigated. Redundant path networks provide significant tolerance to faults at minimal costs; in this paper improvements in performance and very graceful degradation are also shown to result from the availability of redundant paths. A Markov model is introduced for the operation of these networks in the circuit-switched mode and is solved numerically to obtain the performance measures of interest. The structure of the networks that provide maximal performance is also characterized.