A Flexible Image Processor Using Array Elements
CAW '80 The Papers of the Fifth Workshop on Computer Architecture for Non-Numeric Processing
Throughput analysis and configuration design of a shared-resource multiprocessor system: PUMPS
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
IEEE Transactions on Computers
Design of a Raster Display Processor for Office Applications
IEEE Transactions on Computers
Design of a Massively Parallel Processor
IEEE Transactions on Computers
A Parallel Picture Processing Machine
IEEE Transactions on Computers
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This paper presents a multiprocessor system architecture and the scheduling policies of the processors which can off-load a host computer in the image processing of office documents. The objective of this system is to provide extensive image processing capabilities at minimum cost and with an acceptable interactive response time. Multiprocessor system architecture, image partitioning strategies, image processing algorithm characteristics, performance modeling, and processor scheduling policies are investigated. A prototype multiprocessor image processing system has been built at the IBM San Jose Research Laboratory.