A fault tolerant massively parallel processing architecture
Journal of Parallel and Distributed Computing
Efficient construction of catastrophic patterns for VLSI reconfigurable arrays
Integration, the VLSI Journal
Counting the number of fault patterns in redundant VLSI arrays
Information Processing Letters
On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy
Integration, the VLSI Journal
Catastrophic faults in reconfigurable systolic linear arrays
Discrete Applied Mathematics
Testing and reconfiguration of VLSI linear arrays
Theoretical Computer Science
On enumeration of catastrophic fault patterns
Information Processing Letters
Wafer-Scale Integration of Systolic Arrays
IEEE Transactions on Computers
Computer
Fault-tolerant meshes with minimal numbers of spares
SPDP '91 Proceedings of the 1991 Third IEEE Symposium on Parallel and Distributed Processing
| Hi-index | 0.89 |
The catastrophic fault pattern is a pattern of faults occurring at strategic locations that may render a system unusable regardless of its component redundancy and of its reconfiguration capabilities. In this paper, we extend the characterization of catastrophic fault patterns known for linear arrays to two-dimensional VLSI arrays in which all links are unidirectional. We determine the minimum number of faults required for a fault pattern to be catastrophic and give algorithm for the construction of catastrophic fault patterns with minimum number of faults.