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IEEE Transactions on Computers
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Information Processing Letters
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Information Processing Letters
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SIAM Journal on Discrete Mathematics
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Discrete Mathematics - Special issue on graph theory and applications
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Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures
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STOC '00 Proceedings of the thirty-second annual ACM symposium on Theory of computing
Graph separators, with applications
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Area-Efficient VLSI Computation
Area-Efficient VLSI Computation
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ACM Computing Surveys (CSUR)
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GD '96 Proceedings of the Symposium on Graph Drawing
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LATIN'10 Proceedings of the 9th Latin American conference on Theoretical Informatics
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In this paper we consider the VLSI layout (i.e., Manhattan layout) of graphs into grids with minimum width (i.e., the length of the shorter side of a grid)as well as with minimum area. The layouts into minimum area and minimum width are equivalent to those with the largest possible aspect ratio of a minimum area layout. Thus such a layout has merits that, by "folding" the layout, a layout of all possible aspect ratio can be obtained with increase of area within a small constant factor. We show that an N-vertex tree with layout-width (i.e., the minimum width of a grid into which the tree can be laid out) k can be laid out into a grid of area O(N) and width O(k). For binary tree layouts, we give a detailed trade-off between area and width: an N-vertex binary tree with layout-width k can be laid out into area O(k+α/1+αN) and width k+α, where α is an arbitrary integer with 0≤ α≤√N, and the area is existentially optimal for any k≥ 1 and α≥ 0. This implies that α=ω(k) is essential for a layout of a graph into optimal area. The layouts proposed here can be constructed in polynomial time. We also show that the problem of laying out a given graph G into given area and width, or equivalently, into given length and width is NP-hard even if G is restricted to a binary tree.