Efficient embeddings of binary trees in VLSI arrays
IEEE Transactions on Computers
The complexity of minimizing wire lengths in VLSI layouts
Information Processing Letters
Unit-length embedding of binary trees on a square grid
Information Processing Letters
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Embeddings of treelike graphs into 2-dimensional meshes
WG '90 Proceedings of the 16th international workshop on Graph-theoretic concepts in computer science
Sorting and selection arrays with diagonal connections
Proceedings of the first Canada-France conference on Parallel and distributed computing
Embeddings of complete binary trees into grids and extended grids with total vertex-congestion
Discrete Applied Mathematics
Graph Drawing: Algorithms for the Visualization of Graphs
Graph Drawing: Algorithms for the Visualization of Graphs
Optimizing Area and Aspect Ratio in Straight-Line Orthogonal Tree Drawings
GD '96 Proceedings of the Symposium on Graph Drawing
Optimal Embedding of Complete Binary Trees into Lines and Grids
WG '91 Proceedings of the 17th International Workshop
Bounds on minimax edge length for complete binary trees
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
The tree machine: a highly concurrent computing environment
The tree machine: a highly concurrent computing environment
Complexity dichotomy on partial grid recognition
Theoretical Computer Science
Faithful representations of graphs by islands in the extended grid
LATIN'10 Proceedings of the 9th Latin American conference on Theoretical Informatics
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Let Th be the complete binary tree of height h. Let M be the infinite grid graph with vertex set Z2, where two vertices (x1, y1) and (x2, y2) of M are adjacent if and only if |x1-x2| + |y1-y2|= 1. Suppose that T is a tree which is a subdivision of Th and is also isomorphic to a subgraph of M. Motivated by issues in optimal VLSI design, we show that the point expansion ratio n(T)/n(Th) = n(T)/(2h+1 - 1) is bounded below by 1.122 for h sufficiently large. That is, we give bounds on how many vertices of degree 2 must be inserted along the edges of Th in order that the resulting tree can be laid out in the grid. Concerning the constructive end of VLSI design, suppose that T is a tree which is a subdivision of Th and is also isomorphic to a subgraph of the n × n grid graph. Define the expansion ratio of such a layout to be n2/n(Th)=n2/(2h+1 - 1). We show constructively that the minimum possible expansion ratio over all layouts of Th is bounded above by 1.4656 for sufficiently large h. That is, we give efficient layouts of complete binary trees into square grids, making improvements upon the previous work of others. We also give bounds for the point expansion and expansion problems for layouts of Th into extended grids, i.e. grids with added diagonals.