Size-energy tradeoffs for unate circuits computing symmetric Boolean functions

  • Authors:

  • Kei Uchizawa;Eiji Takimoto;Takao Nishizeki

  • Affiliations:

  • Graduate School of Information Sciences, Tohoku University, Sendai 980-8579, Japan;Department of Informatics, Graduate School of Information Science and Electrical Engineering, Kyushu University, Fukuoka 819-0395, Japan;School of Science and Technology, Kwansei Gakuin University, Sanda, 669-1337, Japan

  • Venue:
  • Theoretical Computer Science
  • Year:
  • 2011

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Abstract

A unate gate is a logical gate computing a unate Boolean function, which is monotone in each variable. Examples of unate gates are AND gates, OR gates, NOT gates, threshold gates, etc. A unate circuit C is a combinatorial logic circuit consisting of unate gates. Let f be a symmetric Boolean function of n variables, such as the Parity function, MOD function, and Majority function. Let m"0 and m"1 be the maximum numbers of consecutive 0's and consecutive 1's in the value vector of f, respectively, and let l=min{m"0,m"1} and m=max{m"0,m"1}. Let C be a unate circuit computing f. Let s be the size of the circuit C, that is, C consists of s unate gates. Let e be the energy of C, that is, e is the maximum number of gates outputting ''1'' over all inputs to C. In this paper, we show that there is a tradeoff between the size s and the energy e of C. More precisely, we show that (n+1-l)/m@?s^e. We also present lower bounds on the size s of C represented in terms of n, l and m. Our tradeoff immediately implies that logn@?elogs for every unate circuit C computing the Parity function of n variables.