Balance in architectural design

Authors:
Samuel Ho;Lawrence Snyder
Affiliations:
University of Washington, Seattle, Washington;University of Washington, Seattle, Washington
Venue:
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Year:
1990

Citing 3
Cited 0

Architectural tradeoffs in parallel computer design

Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Area-time complexity for VLSI

STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
Processor element architecture for nonshared memory parallel computers

Processor element architecture for nonshared memory parallel computers

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Abstract

We introduce a performance metric, normalized time, which is closely related to such measures as the area-time product of VLSI theory and the price / performance ratio of advertising literature. This metric captures the idea of a piece of hardware “pulling its own weight,” i.e. contributing as much to performance as it costs in resources. We then prove general theorems for stating when the size of a given part is in balance with its utilization, and give specific formulas for commonly found linear and quadratic devices. We also apply these formulas to an analysis of a specific processor element, and discuss the implications for bit-serial vs word-parallel, RISC vs CISC, and VLIW designs.