Data structures and network algorithms
Data structures and network algorithms
Fourier transform and convolution subroutines for the IBM 3090 Vector facility
IBM Journal of Research and Development
A model for hierarchical memory
STOC '87 Proceedings of the nineteenth annual ACM symposium on Theory of computing
The I/O complexity of sorting and related problems
14th International Colloquium on Automata, languages and programming
ACM Computing Surveys (CSUR)
Storage reorganization techniques for matrix computation in a paging environment
Communications of the ACM
Organizing matrices and matrix operations for paged memory systems
Communications of the ACM
Bibliography and reading on CPU cache memories and related topics
ACM SIGARCH Computer Architecture News
Algorithmic Studies in Mass Storage Systems
Algorithmic Studies in Mass Storage Systems
Data Structures and Algorithms
Data Structures and Algorithms
Introduction to VLSI Systems
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
A layout strategy for VLSI which is provably good (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
I/O complexity: The red-blue pebble game
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Delayed-Staging Hierarchy Optimization
IEEE Transactions on Computers
Evaluation techniques for storage hierarchies
IBM Systems Journal
Determining hit ratios for multilevel hierarchies
IBM Journal of Research and Development
STOC '88 Proceedings of the twentieth annual ACM symposium on Theory of computing
A Blocked All-Pairs Shortest-Path Algorithm
SWAT '00 Proceedings of the 7th Scandinavian Workshop on Algorithm Theory
A Characterization of Temporal Locality and Its Portability across Memory Hierarchies
ICALP '01 Proceedings of the 28th International Colloquium on Automata, Languages and Programming,
Designing Practical Efficient Algorithms for Symmetric Multiprocessors
ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation
FOCS '99 Proceedings of the 40th Annual Symposium on Foundations of Computer Science
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
An Address Dependence Model of Computation for Hierarchical Memories with Pipelined Transfer
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 8 - Volume 09
HPCASIA '05 Proceedings of the Eighth International Conference on High-Performance Computing in Asia-Pacific Region
Combating I-O bottleneck using prefetching: model, algorithms, and ramifications
The Journal of Supercomputing
On the limits of cache-oblivious rational permutations
Theoretical Computer Science
A unified model for multicore architectures
IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
On approximating the ideal random access machine by physical machines
Journal of the ACM (JACM)
psort, Yet Another Fast Stable Sorting Software
SEA '09 Proceedings of the 8th International Symposium on Experimental Algorithms
Brief announcement: low depth cache-oblivious sorting
Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures
Cache-optimal algorithms for option pricing
ACM Transactions on Mathematical Software (TOMS)
Evaluating multicore algorithms on the unified memory model
Scientific Programming - Software Development for Multi-core Computing Systems
Algorithms for memory hierarchies: advanced lectures
Algorithms for memory hierarchies: advanced lectures
Cache-oblivious simulation of parallel programs
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
ACM Transactions on Algorithms (TALG)
Algorithmic ramifications of prefetching in memory hierarchy
HiPC'06 Proceedings of the 13th international conference on High Performance Computing
Practical verified computation with streaming interactive proofs
Proceedings of the 3rd Innovations in Theoretical Computer Science Conference
The potential of on-chip multiprocessing for QCD machines
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
A memory access model for highly-threaded many-core architectures
Future Generation Computer Systems
Computing with Time-Varying Data: Sequential Complexity and Parallel Speed-Up
Theory of Computing Systems
Hi-index | 0.00 |
In this paper we introduce a model of Hierarchical Memory with Block Transfer (BT for short). It is like a random access machine, except that access to location x takes time f(x), and a block of consecutive locations can be copied from memory to memory, taking one unit of time per element after the initial access time. We first study the model with f(x) = xα for 0 1. Finally, we study the model f(x) = log x and obtain optimal bounds of θ(n log*n) for simple problems mentioned above and of θ(n log n) for sorting, computing an FFT graph, and for some permutations.