How to reduce aliasing in linear analog testing

Authors:
Zhen Guo
Affiliations:
New Jersey Institute Of Technology, Newark, NJ
Venue:
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Year:
2004

Citing 3
Cited 0

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Abstract

Aliasing is a difficult problem that needs to be handled carefully, due to its effects on the test quality of analog circuits. In this paper, we first give the evidence of aliasing occurrence in the summation-based method, and then propose the concept of bound curve and derive the bound equation for finding the aliasing-reduced region and we present a case study of how to reduce aliasing. Finally we expand the aliasing study to obtain an optimal sampling frequency.