Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
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Discusses the problem of estimating the sum of the detection probabilities of the yet unobserved faults during a random pattern test of a given digital circuit. The authors describe a statistical method for this purpose. The method requires keeping track of each fault until it is detected for the second time, and thus the simulation cost is about twice the cost of a similar simulation which abandons faults after their first detect. The benefits of having an estimate of the sum of these detection probabilities are twofold: (1) it provides a good stopping rule whenever 100% fault coverage is infeasible (which is often the case), and (2) it provides an estimate of the required effort to detect the next fault. The results of tests performed on some circuits are presented.