Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Shift Register Sequences
Boundary Scan with Built-In Self-Test
IEEE Design & Test
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The design of a pseudorandom pattern generator for a boundary-scan chip with built-in self-test is described. The proposed test-generation procedure, together with a method of connecting the generator outputs and the primary inputs of the chip under test, ensures full pattern coverage. The authors show how to evaluate the choice of generator parameters and initial states when there are more flip-flops in the generator than bits in the test pattern.