Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Fault-tolerant computer system design
Fault-tolerant computer system design
Hierarchical Diagnosis of Identical Units in a System
IEEE Transactions on Computers
Fault Tolerance through Re-Execution in Multiscalar Architecture
DSN '00 Proceedings of the 2000 International Conference on Dependable Systems and Networks (formerly FTCS-30 and DCCA-8)
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We consider designs where the same processing units (orcircuits) appear multiple times. This is prevalent in currentmicroprocessors and in reliable systems. Fault detection insuch designs can be done by comparing output responsesof identical circuits when identical input sequences areapplied to them. The main advantage of this method overother methods of fault detection is that output responsesdo not need to be precomputed, and therefore, arbitrary,unknown input sequences can be used for testing. Wepropose a design-for-testability method for such designsthat applies the same modifications to the states of the circuitsbeing compared. If the circuits are fault free, theycontinue to produce identical output sequences after theirstates are modified in the same way. However, if one ofthe circuits is faulty, state modification can help increasethe distance between the circuit states and eventually contributeto the detection of the fault. The proposed statemodifications can be implemented by using hardware thatsupports assignment statements in the instruction sets ofmicroprocessors. Depending on the state modificationused, the proposed method may be applicable to concurrent,on-line or off-line testing. We present experimentalresults to support the effectiveness of the proposedmethod.