System-level fault diagnosis: A survey
Microprocessing and Microprogramming - Fault tolerant computing
Built-In Testing of Integrated Circuit Wafers
IEEE Transactions on Computers
Hierarchical Probablistic Diagnosis of MCMs on Large-Area Substrates
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Method to Enhance the Fault Coverage Obtained by Output Response Comparison of Identical Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors
IEEE Transactions on Dependable and Secure Computing
| Hi-index | 14.98 |
A hierarchical diagnosis algorithm is presented for testing identical units in a system. As all units are similar, it is essential that the test process be parallelized to enable test of multiple units for the cost of testing one unit. With this objective in mind, we propose a novel test architecture consisting of a hierarchy of testers in a system to test all the units simultaneously. In this approach, special test chips are placed at strategic locations in a system to compute a 驴golden response驴 by analyzing the responses of all units. The responses are propagated up the hierarchy of testers. At each level, the testers analyze the data and pass golden response computation data to testers at higher level. The tester at the top of the hierarchy computes the golden response and the test result is percolated down to the testers at the lowest level that identify faulty and fault-free units. Using this diagnosis approach, almost all units are correctly diagnosed, even when yields are as low as 40 percent. The hardware architecture of all test chips is identical and simple. This approach can be used for testing massively parallel multiprocessor systems, MCMs fabricated on a large area panel, and integrated circuits on silicon wafers.