Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Discrete-time signal processing
Discrete-time signal processing
Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Pseudorandom-pattern test resistance in high-performance DSP datapaths
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Frequency Domain Testing of ADCs
IEEE Design & Test
Towards 100% Testable FIR Digital Filters
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Synthesizing Self-Testable Filters via Scaling and Redundant Operator Elimination
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
Variance mismatch: identifying random-test resistance in DSP datapaths
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
Test quality and fault risk in digital filter datagraph BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Testing digital low-pass filters using oscillation-based test
Microprocessors & Microsystems
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We examine frequency-domain issues in the design and selectionof on-chip test generators for built-in self-test (BIST) of high-performancedigital filters. Test-generator/circuit compatibility isidentified as a significant factor in testing large filters. A fault-injectionexperiment is used to show that when an incompatible testgenerator is used, high fault coverage (over 99%) does not guaranteethat all serious faults will be detected. The frequency-domaincharacteristics of some basic test generation schemes are examined,and guidelines for test generator selection are proposed. Analyticaltechniques for identifying frequency-related testability problemsare discussed, and several test generation schemes are evaluated byfault simulating them against lowpass, bandpass, and highpass filters.A mixed test generation scheme is shown to reduce the numberof untested faults by a factor of two to three over a standard linear-feedbackshift-register (LFSR) based test scheme, at little added cost.