Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
The Design of Rijndael
On analysis and synthesis of (n, k)-non-linear feedback shift registers
Proceedings of the conference on Design, automation and test in Europe
Open problems related to algebraic attacks on stream ciphers
WCC'05 Proceedings of the 2005 international conference on Coding and Cryptography
GPU implementation of a scalable non-linear congruential generator for cryptography applications
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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For secure high data-rate communications, fast key generation algorithms are crucial. In this paper, we present a VLSI implementation of a Non-Linear Feedback Shift Register (NLFSR) for cryptography applications. Unlike existing cryptographic key generation techniques, our NLFSR generates multiple (64 in our implementation) key bits in each clock cycle. This enables its use in secure, high speed communications. Our NLFSR is implemented using a plurality (3 in our implementation) of LFSRs. The outputs of 64 bits from each LFSR are combined using 64 encoded majority functions, where the majority function used for any bit is changed at every clock cycle. We demonstrate that our NLFSR can generate keys which may be used for OC-768 optical fiber communication, which operates at 40 Gbps. The keys from our NLFSR pass all the tests in the NIST suite, which is a defacto benchmark used in industry to evaluate the quality of ciphers.