Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
System Level Interconnect Test in a Tristate Environment
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Test Methodology for VLSI Chips on Silicon
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
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A highly parallel design process is a means to minimize the system design cycle time. Concurrent engineering principles applied to design and test attain dramatic cycle time reduction in systems with structurally tested ICs.