Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Optimal pipelining in supercomputers
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
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Latch-to-latch timing rules that ensure the proper operation of synchronous systems are presented and analyzed. The rules state bounds on the amount of propagation delay for the combinational logic between consecutive latch pairs in a digital design. If the bounds are satisfied in a design, then setup and hold times are met throughout the design for each latch on each cycle of machine operation. The rules are quite general in that they apply to systems with multiple skew levels (a feature of most real systems), with multiple latch parameters such as clock to data propagation delays, data to data propagation delays, and setup and hold times, and with multiple clock pulse widths and clock phases. The abstract notion of a clock skew hierarchy is introduced and characterized. The rules are established by a novel and robust method.