Neural networks in C++: an object-oriented framework for building connectionist systems
Neural networks in C++: an object-oriented framework for building connectionist systems
Practical neural network recipes in C++
Practical neural network recipes in C++
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Dynamic voltage scaling and power management for portable systems
Proceedings of the 38th annual Design Automation Conference
A stream compiler for communication-exposed architectures
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Exploiting coarse-grained task, data, and pipeline parallelism in stream programs
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Accurate and efficient regression modeling for microarchitectural performance and power prediction
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Efficiently exploring architectural design spaces via predictive modeling
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A Predictive Performance Model for Superscalar Processors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Efficient design space exploration for application specific systems-on-a-chip
Journal of Systems Architecture: the EUROMICRO Journal
lmbench: portable tools for performance analysis
ATEC '96 Proceedings of the 1996 annual conference on USENIX Annual Technical Conference
Exploring power management in multi-core systems
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Predictive design space exploration using genetically programmed response surfaces
Proceedings of the 45th annual Design Automation Conference
Journal of Systems Architecture: the EUROMICRO Journal
Machine Learning Models to Predict Performance of Computer System Design Alternatives
ICPP '08 Proceedings of the 2008 37th International Conference on Parallel Processing
Prediction-Based Power-Performance Adaptation of Multithreaded Scientific Codes
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the 46th Annual Design Automation Conference
Accurate and efficient processor performance prediction via regression tree based modeling
Journal of Systems Architecture: the EUROMICRO Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architecture performance prediction using evolutionary artificial neural networks
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
A Safari Through the MPSoC Run-Time Management Jungle
Journal of Signal Processing Systems
A correlation-based design space exploration methodology for multi-processor systems-on-chip
Proceedings of the 47th Design Automation Conference
Proceedings of the Conference on Design, Automation and Test in Europe
Fast multidimension multichoice knapsack heuristic for MP-SoC runtime management
ACM Transactions on Embedded Computing Systems (TECS)
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
IEEE Transactions on Evolutionary Computation
Single- and multiobjective evolutionary optimization assisted by Gaussian random field metamodels
IEEE Transactions on Evolutionary Computation
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Application-specific multicore architectures are usually designed by using a configurable platform in which a set of parameters can be tuned to find the best trade-off in terms of the selected figures of merit (such as energy, delay, and area). This multi-objective optimization phase is called Design-Space Exploration (DSE). Among the design-time (hardware) configurable parameters we can find the memory subsystem configuration (such as cache size and associativity) and other architectural parameters such as the instruction-level parallelism of the system processors. Among the runtime (software) configurable parameters we can find the degree of task-level parallelism associated with each application running on the platform. The contribution of this article is twofold; first, we introduce an evolutionary (NSGA-II-based) methodology for identifying a hardware configuration which is robust with respect to applications and corresponding datasets. Second, we introduce a novel runtime heuristic that exploits design-time identified operating points to provide guaranteed throughput to each application. Experimental results show that the design-time/runtime combined approach improves the runtime performance of the system with respect to existing reference techniques, while meeting the overall power budget.