GALS-CMP: chip-multiprocessor for GALS embedded systems

Authors:
Muhammad Nadeem;HeeJong Park;Zhenmin Li;Morteza Biglari-Abhari;Zoran Salcic
Affiliations:
Department of Electrical & Computer Engineering, University of Auckland, Auckland, New Zealand;Department of Electrical & Computer Engineering, University of Auckland, Auckland, New Zealand;Department of Electrical & Computer Engineering, University of Auckland, Auckland, New Zealand;Department of Electrical & Computer Engineering, University of Auckland, Auckland, New Zealand;Department of Electrical & Computer Engineering, University of Auckland, Auckland, New Zealand
Venue:
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
Year:
2013

Citing 8
Cited 0

Communicating sequential processes

Communicating sequential processes
A Java processor architecture for embedded real-time systems

Journal of Systems Architecture: the EUROMICRO Journal
SystemJ compilation using the tandem virtual machine approach

ACM Transactions on Design Automation of Electronic Systems (TODAES)
JOP Reference Handbook: Building Embedded Systems with a Java Processor

JOP Reference Handbook: Building Embedded Systems with a Java Processor
A real-time Java chip-multiprocessor

ACM Transactions on Embedded Computing Systems (TECS)
SystemJ: A GALS language for system level design

Computer Languages, Systems and Structures
RJOP: a customized Java processor for reactive embedded systems

Proceedings of the 48th Design Automation Conference
GALS-JOP: A Java Embedded Processor for GALS Reactive Programs

DASC '11 Proceedings of the 2011 IEEE Ninth International Conference on Dependable, Autonomic and Secure Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper we present a novel multi-processor architecture for concurrent execution of programs that follow the Globally Asynchronous Locally Synchronous (GALS) formal model of computation. Programs are specified using the SystemJ concurrent programming language, suitable for modeling heterogeneous embedded applications that contain reactive and control driven parts and interact with the external environment. The proposed architecture is based on separating the control-driven and data-driven operations and executing them on distinct cores that support both types of operations, implemented as two modes within the single processor core. Each core can switch between two modes without any overhead. The core as the basic building block of the multiprocessor extends Java Optimized Processor (JOP), suitable for data-driven transformational operations, with control-oriented constructs that implement concurrency, reactivity, and control flow in SystemJ. Experimental evaluation over a range of benchmarks shows significant performance improvements over the existing platforms developed for the execution of the SystemJ program.