Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems

Authors:
Pascal Andreas Meinerzhagen;Onur Andiç;Jürg Treichler;Andreas Peter Burg
Affiliations:
EPFL, Lausanne, Switzerland;ETHZ, Zurich, Switzerland;ETHZ, Zurich, Switzerland;EPFL, Lausanne, Switzerland
Venue:
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Year:
2011

Citing 4
Cited 0

A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing

MTDT '03 Proceedings of the 2003 International Workshop on Memory Technology, Design and Testing
Let's Think Analog

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
CMOS Digital Integrated Circuits Analysis & Design

CMOS Digital Integrated Circuits Analysis & Design
Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication

Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper considers the problem of increasing the storage density in fault-tolerant VLSI systems which require only limited data retention times. To this end, the concept of storing many bits per memory cell is applied to area-efficient and fully logic-compatible gain-cell-based dynamic memories. A memory macro in 90-nm CMOS technology including multilevel write and read circuits is proposed and analyzed with respect to its read failure probability due to within-die process variations by means of Monte Carlo simulations.