Operation and Modeling of the Mos Transistor (The Oxford Series in Electrical and Computer Engineering)
Impact of MOSFET parameters on its parasitic capacitances
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Impact of MOSFET's performance on its threshold voltage and its influence on design of MOS inverters
WSEAS Transactions on Systems and Control
The impact of MOSFET's physical parameters on its threshold voltage
MINO'07 Proceedings of the 6th conference on Microelectronics, nanoelectronics, optoelectronics
Microelectronic Circuits Revised Edition
Microelectronic Circuits Revised Edition
Optimization and process variation analysis of nano-scale transistors
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
Digital Integrated Circuits: Analysis and Design, Second Edition
Digital Integrated Circuits: Analysis and Design, Second Edition
Implementing of neuro-fuzzy system with high-speed, low-power CMOS circuits in current-mode
MINO'10 Proceedings of the 9th WSEAS international conference on Microelectronics, nanoelectronics, optoelectronics
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The pseudo-NMOS logic can be used in special applications to perform special logic function. The pseudo- NMOS logic is based on designing pseudo-NMOS inverter which functions as a digital switch. During the design phase of pseudo-NMOS inverters and logic gates based on MOS technologies, it is necessary to take into consideration many parameters which characterise MOS transistors, which impact static and dynamic performances of the different logic gates. The aim of this paper is to research impact the NMOS (driver) and PMOS (active load) transistors parameters during the design phase of pseudo-NMOS inverters and in design phase pseudo-NMOS logic gates for different work cases. The results obtained emphasize the impact of each single parameter of MOSFET transistor at the low output level state, at the level values of static current at output, on the shape of the voltage transfer characteristic in the pseudo-NMOS inverter, on propagation delays during transition logic state, and impact in pseudo-NMOS logic gates. By adjusting the parameters values of NMOS and PMOS transistor it's possible to design pseudo-NMOS inverters and pseudo-NMOS logic gate which will have acceptable performance depending on designers' requests.