Designing CMOS/molecular memories while considering device parameter variations
ACM Journal on Emerging Technologies in Computing Systems (JETC)
High-Speed Fixed Memories Using Large-Scale Integrated Resistor Matrices
IEEE Transactions on Computers
Worst-Case Analysis of a Resistor Memory Matrix
IEEE Transactions on Computers
Nonvolatile memristor memory: device characteristics and design implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Nondegeneracy conditions for active memristive circuits
IEEE Transactions on Circuits and Systems II: Express Briefs
A Novel Reference Scheme for Reading Passive Resistive Crossbar Memories
IEEE Transactions on Nanotechnology
Memristor Applications for Programmable Analog ICs
IEEE Transactions on Nanotechnology
2T-1R STT-MRAM memory cells for enhanced on/off current ratio
Microelectronics Journal
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A 2 × 2 equivalent statistical circuit model is presented to deal with sneak currents and random data distributions for n × m passive memory arrays of memristive devices. The data-dependent 2 × 2 circuit model enables a broad range of analysis, such as the optimum detection voltage margin, with computational efficiency and has no limit on the memory array size. In addition, we propose replica-based self-adaptable sense resistors to achieve both low-power reading and large voltage detection windowing.