Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Nanowire addressing with randomized-contact decoders
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Assembling nanoscale circuits with randomized connections
IEEE Transactions on Nanotechnology
Nanowire addressing with randomized-contact decoders
Theoretical Computer Science
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Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with CMOS circuits, nanowire decoders were invented. Due to the stochastic nature of the nanoscale fabrication, the decoder addresses that address the nanowires selectively must be generated after fabrication. In this paper, we develop a mathematical model of the nanowire decoders for the generation of the proper addresses. Assuming a simple testing approach calledon-off measurement, we prove that the maximum number of the proper addresses can be generated in finite time. We design the algorithms to generate the required number of the proper addresses. Experimental results confirm the efficiency of our algorithms.