Design trade-offs for high density cross-point resistive memory

Authors:
Dimin Niu;Cong Xu;Naveen Muralimanohar;Norman P. Jouppi;Yuan Xie
Affiliations:
The Penn State University, University Park, PA, USA;The Penn State University, University Park, PA, USA;HP Labs, Palo Alto, CA, USA;HP Labs, Palo Alto, CA, USA;The Penn State University, University Park, PA, USA
Venue:
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Year:
2012

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Abstract

With conventional memory technologies approaching their scaling limit, the search for a new technology has gained increased attention in the recent years. Resistive RAM (ReRAM), with its superior write latency and energy, small cell size (4F2 for a single level cell, F is the feature size), and support for 3D stacking, has been a promising candidate among emerging memory technologies. A key advantage of ReRAM comes from its non-linear nature, which enables a cross-point array structure without having a dedicated access transistor for each cell. While the cross-point structure is effective in improving the memory density, it has inherent disadvantages which introduce extra design challenges. Based on the device characteristics, we perform a comprehensive analysis of issues related to reliability, energy consumption, area overhead, and performance of the cross-point arrays. In addition to the cell-level analysis, we discuss different programming schemes specifically suited for cross-point arrays. We then study the area, energy, and bandwidth of a 256Mbits ReRAM macro in detail for various write schemes. The simulation results enable designers to identify the most performance/energy/area efficient ReRAM organization and cell parameters that meet specific design goals early in the design stage.