IEEE Spectrum
3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
The bleak future of NAND flash memory
FAST'12 Proceedings of the 10th USENIX conference on File and Storage Technologies
Revisiting storage for smartphones
FAST'12 Proceedings of the 10th USENIX conference on File and Storage Technologies
Design trade-offs for high density cross-point resistive memory
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Physically addressed queueing (PAQ): improving parallelism in solid state disks
Proceedings of the 39th Annual International Symposium on Computer Architecture
An Out-of-Core Eigensolver on SSD-equipped Clusters
CLUSTER '12 Proceedings of the 2012 IEEE International Conference on Cluster Computing
An Out-of-Core Dataflow Middleware to Reduce the Cost of Large Scale Iterative Solvers
ICPPW '12 Proceedings of the 2012 41st International Conference on Parallel Processing Workshops
Revisiting widely held SSD expectations and rethinking system-level implications
Proceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems
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Resistive Random Access Memory (RRAM) is a promising next generation non-volatile memory (NVM) technology, thanks to its performance potential, endurance and ease-of-integration with standard silicon CMOS processes. While prior work has evaluated RRAM as a replacement for DRAM or even cache memory, to our knowledge there is no prior study that has investigated whether RRAM could be a viable NAND flash replacement in building large-scale storage-class memory systems. Motivated by this observation, our paper first discusses and quantifies the main problems associated with RRAM that prevent it from replacing NAND flash. The main solution we propose, "slab-based memory access with local/global bitlines," enables dense RRAM islands but can also cause performance related problems. To compensate for the latter, we also propose exploiting internal resource parallelism in RRAM and employing optimized data movement interfaces. Our extensive experimental evaluation using a cycle-level NVM simulator and real workloads under diverse computing domains indicate that the proposed architecture can provide 2.95 ~ 8.28 times better bandwidth and 66% ~ 88% shorter latency as compared to the conventional NAND flash, and improve the system-level performance of our workloads by 5x, with a storage capacity similar to that of the state-of-the-art NAND flash.