Online multiple error detection in crossbar nano-architectures
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Online detection of multiple faults in crossbar nano-architectures using dual rail implementations
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Nanoscale technologies: prospect or hazard to dependable and secure computing?
LADC'07 Proceedings of the Third Latin-American conference on Dependable Computing
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Programmable logic arrays (PLA), which can implement arbitrary logic functions in a two-level logic form, are promising as platforms for nanoelectronic logic due to their highly regular structure compatible with the nano crossbar architectures. Reliability is an important challenge as far as nanoelectronic devices are concerned. Consequently, it is necessary to focus on the fault tolerance aspects of nanoelectronic PLAs to ensure their viability as a foundation for nanoelectronic systems. In this paper, we investigate two types of fault tolerance techniques for nanoelectronic device based PLAs, focusing at the online faults occurring at the cross-points of nano devices. We develop a scheme to precisely locate the faults online, as this is a crucial step for efficient online reconfiguration based fault tolerance schemes. We also propose a tautology based fault masking scheme. We demonstrate that these two types of fault tolerance schemes developed for nano PLAs significantly improve at low hardware cost the reliability of the high fault occurrence nanoelectronic environment.