A new technique of multi-layer thermal analysis for VLSI chips

Authors:
Keiji Nakabayashi;Kazuo Nakajima;Hajimu Iida
Affiliations:
Graduate School of Information Science, Nara Institute of Science and Technology, Nara, Japan;Dept. of Electrical and Computer Engineering, University of Maryland, College Park, MD;Graduate School of Information Science, Nara Institute of Science and Technology, Nara, Japan
Venue:
MMACTEE'07 Proceedings of the 9th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
Year:
2007

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Abstract

We propose a new technique of two dimensional, steady-state thermal analysis for VLSI chips. It can be applied to an analysis model described by a combination of Laplace and Poisson equations for multiple layers of materials. We explain the technique using a simplified model of four layer materials. Our experimental results show that it achieved 70 times speed-up, 3 times memory usage reduction, and an order of magnitude lower residual as compared to the most efficient direct method of LU decomposition. They also reveal the superiority of our technique over the most effective iterative method of ICCG with up to 3 times speed-up and 1.8 times memory usage reduction.