Faster, parametric trajectory-based macromodels via localized linear reductions
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Poor man's TBR: a simple model reduction scheme
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Advances in variation-aware modeling, verification, and testing of analog ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Automated abstraction of large analog circuits greatly improves simulation time in custom analog design flows. Due to the high degree of variety of circuits this task is mainly a manual ad-hoc approach. This paper proposes an automated modeling approach for large scale analog circuits that produces compact expressions from a SPICE netlist. The presented method builds upon the state-of-the-art Trajectory PieceWise (TPW) approach. Because of their data-driven nature, TPW implementations generate models that require on-the-fly database interpolation during simulation, which is not embedded in a standard commercial design flow. Our approach solves this by recombining TPW samples as a surface in a mixed state space-frequency domain, revealing information about the circuit's nonlinear behavior. The resulting data, termed Transfer Function Trajectories (TFT), is fitted with a parametric vector fitting algorithm and further translated to system blocks. These are compatible with VHDL-AMS/Verilog-AMS, Matlab/Simulink or hand calculations at all design stages. The models show high accuracy and a speedup of 10X -- 40X against the ELDO simulator for large circuits up to 150 nodes.