Osculating Thevenin model for predicting delay and slew of capacitively characterized cells
Proceedings of the 39th annual Design Automation Conference
Integration, the VLSI Journal
| Hi-index | 0.00 |
Accurate gate-level static timing analysis in the presenceof RC loads has become an important problem formodern deep-submicron designs. Non-capacitive loadsare usually analyzed using the concept of an effectivecapacitance, Ceff. Most published algorithms for Ceff,however, require special cell characterization orsupplemental information that is not part of standardtiming libraries. In this paper we present a novel Ceffalgorithm that is strictly compatible with existing timinglibraries. It is also fast, easily implemented, and quiteaccurate - within 3% of transistor-level simulation in ourtests. The method is based on approximating a gate by acurrent source, estimating the delay difference when thegate drives the actual RC load and a referencecapacitor, and then converting the delay discrepancyinto a Ceff value. Central to carrying out this program isthe innovative concept of delay correction transferfunction.