DFT of the Cell Processor and its Impact on EDA Test Softwar

Authors:
Louis Bushard;Nathan Chelstrom;Steven Ferguson;Brion Keller
Affiliations:
IBM Corp., Rochester MN;Intrinsity, Austin, TX;IBM Corp., Austin, TX;Cadence Design Systems Inc., Endicott, NY
Venue:
ATS '06 Proceedings of the 15th Asian Test Symposium
Year:
2006

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Abstract

This paper describes aspects of the CELL processor DFT and its effects on the EDA software used to process it. The CELL processor is a very complex multi-core design, and the use of high frequency clocks near 4 GHz drove DFT decisions that had significant implications on several levels. The processor had to support Logic BIST, Memory BIST, OPMISR+, SerDes I/O-WRAP as well as traditional scan-based ATPG all using a freerunning high-speed clock.