Algorithms for detailed placement of standard cells
Proceedings of the conference on Design, automation and test in Europe
Analytical minimization of half-perimeter wirelength
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Analytical power/timing optimization technique for digital system
DAC '77 Proceedings of the 14th Design Automation Conference
Implementation and extensibility of an analytic placer
Proceedings of the 2004 international symposium on Physical design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
| Hi-index | 0.00 |
We present a method to achieve nearly legal placement while optimizing the traditional metrics in an analytical placement framework. A legalization penalty function term is added to the cost function of the placer. The purpose of this term is to remove overlaps and place cells into rows. The new term kicks in when global spreading cannot resolve overlaps any further. We study how this legalization term in placement helps to achieve better final placements when it is used in combination with wire-length driven analytical placement. Experimental results show that using this additional legalization cost term results in reduction of degradation of wire-length from 7.6% to 0.7% after discrete detailed placement. Optimization of wire-length along with the legalization term in placement shows 6% improvement in total wire-length on average, which if translated into timing is 48% of total negative slack. A further feature to control cell density helps reduce congestion by 33%.