Convergence of placement technology in physical synthesis: is placement really a point tool?

• Authors: Ravi Varadarajan
• Venue: Proceedings of the 2003 international symposium on Physical design
• Year: 2003

In this talk, I will analyze the role of placement technology in Physical synthesis. Placement has long been recognized as an important and critical step in the physical synthesis flow. The Placement problem has been researched for the past thirty years and major advancements have been made on this topic. However, most work has focused on placement technology as a point tool.I would like to start off by motivating the need for convergence of placement techniques in two related aspects of the Physical design flow. First, in the RTL or gate level prototyping/floorplanning stage, there is a need for the unification of macro placement and standard cell placement techniques. This requires a placement engine that can operate on a flexible data model. A data model that can simultaneously represent and manipulate objects such as "hard" or "soft" macros, "flexible" clusters or "blobs" of gates or individual standard cells.Second, in the traditional block implementation or "flat physical synthesis" phase, there is a need for convergence of placement, timing analysis and logic optimization. Legacy physical synthesis flows start with a gate level netlist and perform initial timing driven placement. This is followed by in-place optimization of the design where the placed design is optimized by considering transforms such as buffering and gate sizing. In the proposed flow, placement and logic optimization are truly interleaved, which in almost all cases produces a better timing convergence result than the conventional flow. Moreover, there is a strong relation between the above two scenarios in developing a robust Chip level Physical Synthesis syste.In conclusion, even though there can be further research done on new placement algorithms, it makes more sense on using the existing research and concentrating on producing better and robust physical synthesis flows, flows that can perform both as prototyping/floorplanning environments in the front end and implementation environments in the back end.