Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
EURO-DAC '94 Proceedings of the conference on European design automation
Perfect-balance planar clock routing with minimal path-length
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
EURO-DAC '94 Proceedings of the conference on European design automation
Bounded-skew clock and Steiner routing under Elmore delay
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Practical Bounded-Skew Clock Routing
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Proceedings of the 14th ACM Great Lakes symposium on VLSI
On structure and suboptimality in placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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We give the first single-layer clock tree construction with exact zero skew according to the Elmore delay model. The previous Linear-Planar-DME method guarantees a planar solution under the linear delay model. In this paper, we use a Linear-Planar-DME variant connection topology to construct a low-cost zero skew tree (ZST) according to the Elmore delay model. While a linear-delay ZST is trivially converted to an Elmore-delay ZST by “detouring” wires, the key idea is to defer this detouring as much as possible to reduce tree cost. Costs of our planar ZST solutions are comparable to those of the best previous non-planar ZST solutions, and substantially improve over previous planar clock routing methods.