A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning

Authors:
Hidenori Sato;Akira Onozawa;Hiroaki Matsuda
Affiliations:
NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi-shi, Kanagawa Pref., 243-01, Japan;NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi-shi, Kanagawa Pref., 243-01, Japan;NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi-shi, Kanagawa Pref., 243-01, Japan
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

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Abstract

A clock routing technique using a balanced-mesh routing is proposed, which incorporates the advantages of both the well-known balanced-tree and fixed-mesh routing method. The circuit is partitioned into sub-blocks called Mesh-Routing Regions(MR's) in which clock skew is suppressed below a constant by mesh routing. Then the net from the clock source to each MR is routed as a balanced-tree. In using the technique to the design of MPEG2-encoder LSI, a skew of 210~ps was achieved.