Source/drain optimization of underlapped lightly doped nanoscale double-gate MOSFETs

Authors:
D. H. Tassis;A. Tsormpatzoglou;C. A. Dimitriadis;G. Ghibaudo;G. Pananakakis;N. Collaert
Affiliations:
Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece;Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece;Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece;IMEP, MINATEC, Parvis Louis Néel, 38054 Grenoble Cedex 9, France;IMEP, MINATEC, Parvis Louis Néel, 38054 Grenoble Cedex 9, France;IMEC, Kapeldreef 75, 3001 Heverlee, Belgium
Venue:
Microelectronic Engineering
Year:
2010

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Abstract

The impact of the spacer length at the source (L"s) and drain (L"d) on the performance of symmetrical lightly-doped double-gate (DG) MOSFET with gate length L=20nm is analyzed, with the type and doping concentration of the spacers kept the same as in the channel material. Using the transport parameters extracted from experimental data of a double-gate FinFET, simulations were performed for optimization of the underlapped gate-source/drain structure. The simulation results show that the subthreshold leakage current is significantly suppressed without sacrificing the on-state current for devices designed with asymmetrical source/drain extension regions, satisfying the relations L"s=L/2 and L"d=L. In independent drive configuration, the top-gate response can be altered by application of a control voltage on the bottom-gate. In devices with asymmetrical source/drain extension regions, simulations demonstrate that the threshold voltage controllability is improved when the drain extension region length is increased.