Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design and implementation of real time secured RS232 link for multiple FPGA communication
Proceedings of the 2011 International Conference on Communication, Computing & Security
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The main aspects of the design and test (D&T) of a reconfigurable architecture for the Data Acquisition Electronics (DAE) system of the Clear-PEM detector are presented in this paper. The application focuses medical imaging using a compact PEM (positron Emission Mammography) detector with 12288 channels, targeting high sensitivity and spatial resolution. The DAE system processes data that comes from a front-end (FE) electronics identifies the relevant data and transfers it to a PC for image processing. The design is supported in a novel D&T methodology, in which hierarchy, modularity and parallelism are extensively exploited to improve design and testability features. Parameterization has also been used to improve design flexibility. Nominal frequency is 100 MHz. The DAE must respond to a data acquisition rate of 1 million relevant events (coincidences) per second, under a total single photon background rate in the detector of 10 MHz. Trigger and data acquisition logic is implemented in eight 4-million, one 2- million and one I-million gate FPGAs (Xilinx Virtex II). Functional Built-In Self Test (BIST) and Debug features are incorporated in the design to allow on-board FPGA testing and self-testing during product lifetime.