Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture

  • Authors:

  • Shervin Sharifi;Mohammad Hosseinabadi;Pedram Riahi;Zainalabedin Navabi

  • Affiliations:

  • -;-;-;-

  • Venue:
  • DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
  • Year:
  • 2003

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Abstract

Time, power and data volume are among the most challenging problems in test of System-on-Chip (SoC) devices. These problems become even more important in scan-based test. TheSelective Trigger Scan architecture introduced in this paper addresses these problems. Thisarchitecture reduces switching activity in circuit-under-test (CUT) and increases the scan clock frequency. Format of data for this reduced activity architecture enables us to perform a good compression and further reduce the test time. Our experiments on ISCAS 85 and 89 benchmark circuits show effectiveness of this architecture in improving SoC test in terms of power, time and data volume.