Multilayer feedforward networks are universal approximators
Neural Networks
Parallel distributed processing: explorations in the microstructure of cognition, vol. 1: foundations
Practical neural network recipes in C++
Practical neural network recipes in C++
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
IC Defects-Based Testability Analysis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
A circuit level fault model for resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a new bridge fault model that is based on a multiple layer feedforward neural network and implemented within the framework of a VHDL saboteur cell. Empirical evidence and experimental results show that it satisfies a prescribed set of bridge fault model criteria better than existing approaches. The new model computes exact bridged node voltages and propagation delay times with due attention to surrounding circuit elements. This is significant since, with the exception of full analog simulation, no other technique attempts to model the delay effects of bridge defects. Yet, compared to these analog simulations, the new approach is orders of magnitude faster and achieves reasonable accuracy; computing bridged node voltages with an average error near 0.006 volts and propagation delay times with an average error near 14 ps.