Asynchronous circuits based on multiple localised current-sensing completion detection

Authors:
E. Grass;S. Jones
Affiliations:
-;-
Venue:
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Year:
1995

Citing 4
Cited 1

Principles of CMOS VLSI design: a systems perspective

Principles of CMOS VLSI design: a systems perspective
Data flow computing: theory and practice

Data flow computing: theory and practice
Self-timed logic using current-sensing completion detection (CSCD)

Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Digital Hardware Testing: Transistor-Level Fault Modeling and Testing

Digital Hardware Testing: Transistor-Level Fault Modeling and Testing

Activity-Monitoring Completion-Detection (AMCD): A New Single Rail Approach to Achieve Self-Timing

ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems

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Abstract

Asynchronous circuits based on Current-Sensing Completion Detection (CSCD) are an efficient alternative to known dual rail coding techniques in terms of area required, operating speed and power consumption. New BiCMOS Current-Sensing Circuits (CSC's) which fully support the advantages of CSCD are presented. Multiple localised CSC's are studied and an example of a 4-bit parallel multiplier is investigated on different levels of granularity.