A novel multiple-valued CMOS flip-flop employing multiple-valued clock

  • Authors:

  • Yin-Shui Xia;Lun-Yao Wang;A. E. A. Almaini

  • Affiliations:

  • School of Engineering, Napier University, Edinburgh, U.K. and School of Information and Engineering Science, Ningbo University, Ningbo, P.R. China;School of Information and Engineering Science, Ningbo University, Ningbo, P.R. China;School of Engineering, Napier University, Edinburgh, U.K.

  • Venue:
  • Journal of Computer Science and Technology
  • Year:
  • 2005

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Abstract

A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.